1. Field of the Invention
The present invention concerns a process and device for deterministic transmission of asynchronous data in packets.
2. Discussion of the Background
In devices of the prior art for deterministic transmission of asynchronous data in packets, the acquisition device and data acquired by this device are asynchronous. Data packeting is made according to an inherent sequencing. A packet corresponds to one or several acquired data processed with or without wrapping, the wrapping being made up of a heading and an end. The number of data transmitted in the output message corresponding to a packet is defined according to two criteria:
the number of data is restricted:                it is always the same, or        the maximum is specified        
the distribution of data is positioned temporally in an equally-timed manner or not.
In the first example of data transmission from a packet i in the output message, as illustrated in FIG. 1, the number of data Mi is always the same, and distributed in an equally-timed manner (Ti equal delays).
In the second example of data transmission from a packet i in the output message, as illustrated in FIG. 2, the maximum number of data Mi is always the same, it is MxTxi over an identified period of time Txi, and distributed unequally-timed (Txi variable delays)—MxTxi varies at each Txi, with MxTxi≦Mi.
In the field of data acquisition and telemetry of flight testing installations, the numerical or digital data, conveyed on continuous and cyclic messages, issued by acquisition and processing systems of the prior art is stored in the FIFO (First in-First out) batteries as and when it arrives. The data arrives in a totally asynchronous manner.
A module for packeting facilitates placing certain data from these FIFO batteries according to a predefined order. It also facilitates enhancing this data with elements of the relative date calculation type, data identification, and formatting of data, etc. A packet thus obtained is therefore a group of data with a precise format and containing data in a precise order.
A module for packeting operates according to the following succession of stages:                1) reception of data contained in the FIFO batteries (dump),        2) start of packeting,        3) packeting, with sorting and data enhancement,        4) end of packeting,        5) sending of the packet to a message composition module.        
This message composition module recovers, one after the other, the packets created by the packeting modules. A message is then made up of successive packets in a predefined order.
A formatting module then facilitates setting the message in electrical format in the protocol used for the transmission.
The operating cycle of the packeting module is self-sustaining. When the message composition module needs a packet, it sends a request to the packeting module which transmits the packet if it is made up, i.e. if stage 4 is finished. If not, it sends nothing or else an empty packet so as not to block the message composition module. The data is transmitted via the various stages 1 to 5—the data arrives, it is put into packets by a self-sustaining device which has its own life, as it is only transferred in the message if the packet is ready. The message can contain no data, solely because the packeting has not been finished.
In these devices of the prior art, the data conveyed on the messages is at fixed slots in time. They are PCM (Pulse Coded Modulation) type messages which meet the IRIG106 standard. The formalism of packeting, as a packet can be made up of one datum, is standardized. On the other hand, this standard stipulates nothing on the transmission time of the packets. It is the same for the CE83 and CCSDS standards.
As illustrated in FIG. 3, the data and transmission in the output message are asynchronous, the transmission time TT therefore varies between the time of packeting TP and a duration 2*TP equal to twice this time, as the transmission time in the output message TMS is such that TMS<<TP.